preliminary product brief august 2000 HW3100/hw2000 home wire tm home phoneline networking chip set chip set features n turnkey solution for pci adapter cards n support for the homepna * interface specification 2.0: adaptive rate selection: 1 mbit/s to 16 mbits/s n compliant with homepna phy specification revi- sion 1.1: integrated 1 mbit/s phy on the HW3100 automatically selects between homepna 1.1/ 2.0 modulation and protocol based on capabili- ties of partner station on the network n highly integrated home phoneline networking chip set with an ieee ? 802.3-compliant 10/100 mbits/s media access controller (mac): HW3100 homepna /modem controller hw2000 analog front end (afe) n support for multimedia and real-time applications using priority-based queuing quality of service (qos): implements eight levels of packet priority n compatible with existing services: voice v.90 and emerging v.92 analog modems g.lite splitterless dsl (g.992.2) full-rate dsl (g.992.1) isdn n highly integrated hw2000 afe: support for all homepna 2.0 front-end transmit and receive operations minimal additional components required 10-bit adc and dac integrated crystal oscillator: 28 mhz fundamen- tal mode crystal on-chip filtering n ieee 802.3 (ethernet)-compliant media access controller (mac): address filtering: unicast, multicast, broadcast, and promiscuous mode tx and rx packet status information n bus mastering architecture with integrated tx and rx direct memory access (dma) controllers and buffer management for efficient cpu utilization n independent transmit and receive fifos with pro- grammable thresholds buffer can accommodate 3.5 maximum size ethernet packets user-programmable tx and rx buffer sizes n low-power, 3.3 v, 0.20 m technology pci features n glueless peripheral component interconnect (pci) interfaces: 5.0 v and 3.3 v signaling n compliant with pci bus specification, revision 2.2 power management features n compliant with the network device class power management specification, revision 1.0a, as defined in the pc99 hardware design guide n compliant with pci bus power management inter- face specification, revision 1.1 n supports the advanced configuration and power interface (acpi) specification, revision 1.0 * homepna is an acronym for home phoneline networking alli- ance. it is a trademark of homepna, inc. ? ieee is a registered trademark of the institute of electrical and electronics engineers, inc.
2 2 lucent technologies inc. HW3100/hw2000 home wire preliminary product brief home phoneline networking chip set august 2000 chip set features (continued) modem interface features n provides line serial input/output (lsio) interface for v.90/v92 host-controlled modem support: silicon daa interface n compliant with the device class specification as defined in the pc99 hardware design guide: wake-on-ring support additional chip set features n serial eeprom interface n led support: link activity tx activity rx activity collision detect carrier sense n microsoft windows* 9x, windows 2000, and win- dows nt * 5.0 driver support n ieee 1149.1 compliant jtag test access port description the lucent technologies microelectronics groups HW3100/hw2000 home wire home phoneline net- working chip set is a fully integrated, turnkey solution designed to provide high-speed networking over exist- ing residential telephone wiring. the home wire chip set provides automatic rate adap- tation, instantaneously adjusting to the changing elec- trical characteristics of the home phoneline communications channel, in order to select the optimal speed which can reach a maximum of 16 mbits/s. * microsoft, windows, and windows nt are registered trademarks of microsoft corporation. the two-device HW3100/hw2000 home wire chip set fully supports the homepna interface specification 2.0. the homepna was formed to develop specifica- tions for interoperable, home-networked devices that use the already-in-place residential telephone wiring, regardless of the topology. the chip set is also fully compliant with the homepna phy specification revi- sion 1.1, in order to provide backwards compatibility with existing applications and home networks built around the homepna 1.1 technology. in order to provide a robust, cost-effective, and simple- to-use home phoneline networking solution, the home wire chip set leverages the existing ieee 802.3 mac protocol and existing plug and play tcp/ip based net- working software stacks used in the windows 95, 98, and windows nt operating systems. up to 25 pcs, peripherals, or network devices can be installed on a single home phoneline network that can span up to 1000 feet between the two farthest points. the HW3100/hw2000 home wire chip set is fully compatible with existing phone services such as voice, facsimile, v.90/v.92 modem connections, isdn voice and data, and adsl. products based on the home wire chip set will not compromise or interrupt any of these services. frequency division multiplexing (fdm) technology is used to simultaneously support existing and emerging telephone services along with networked homepna data traffic. the frequency ranges for homepna based products have been carefully selected to avoid interference from these various ser- vices that may be encountered in a typical home. as shown in figure 1, signals from the home wire chip set are centered at 7 mhz, with the signal ranging from 4.25 mhz to 9.75 mhz. this frequency range is well above the frequencies used for existing phone ser- vices.
lucent technologies inc. 3 preliminary product brief HW3100/hw2000 home wire august 2000 home phoneline networking chip set description (continued) 5-8802.r3 figure 1 . home wire chip set compatibility with existing services 4 khz 4.25 mhz 26 khz 552 khz 2 mhz 9.75 mhz voice/v.90/v.92 adsl g.lite home phoneline frequency ( homepna ) networking the home wire chip set unleashes the power of net- working in the home by enabling a host of applications, allowing users to maximize their investment in periph- eral devices, and take full advantage of existing narrow- band or future broadband connections. the home wire chip set supports multimedia and real-time applications using priority-based queuing to ensure quality of ser- vice (qos), enabling such applications as voice and video over ip in the home. the home wire chip set pro- vides the core technology for the following: n internet connection sharing n peripheral sharing (i.e., printers, scanners, etc.) n file and application sharing n entertainment (i.e., multiplayer gaming) n home automation n ip telephony n video over ip n pc-to-pc intercom n residential gateways the HW3100/hw2000 home wire chip set also has provisions to support either a line codec or silicon daa enabling the use of v.90/v.92 host-controlled modem technology. v.90/v.92 host-controlled modem technology has been enabled by the availability of ample processing power in todays pcs. v.90/v.92 host-controlled modem tech- nology eliminates the need for a dedicated digital signal processor to perform the specialized telephone line sig- nal processing functions; the host processor assumes this function. with the home wire chip set, v.90/v.92 modem func- tionality can be easily added to the design, eliminating the need for a separate pci-based modem. a precious pci slot is also freed up and the overall system cost is significantly reduced. in addition, the use of a silicon daa with the home wire chip set reduces the overall cost, since a significant number of discrete compo- nents can be eliminated. the home wire chip set is also compliant with the pc99 specification and the pci bus power manage- ment interface specification.
HW3100/hw2000 home wire preliminary product brief home phoneline networking chip set august 2000 4 lucent technologies inc. functional description the HW3100/hw2000 home wire chip set consists of the lucent HW3100 homepna /modem controller and the hw2000 analog front end (afe). the HW3100 integrates the following functional blocks: an ieee 802.3 media access controller (mac), a homepna 1.1 phy, a pci interface, independent transmit and receive fifos, separate tx and rx bus mastering dma controllers, a serial eeprom interface, and a line serial i/o (lsio) interface for v.90/v.92 host-controlled modem applications. the hw2000 provides the line interface, on-chip tx and rx filtering, an analog-to-digital converter (adc), and a digital-to-analog converter (dac). 5-8804.f figure 2. home wire chip set pci with v.90/v.92 host-controlled modem system block diagram figure 2 is a block diagram of a pci-based home wire solution that provides homepna 2.0 functionality and a v.90/v.92 host-controlled modem. interactions between the host system and the home wire chip set occur in two modes: programmed i/o (pio) and bus master modes. in the pio mode, the host can read and write to the hw3130s control and status registers using either direct or memory mapped i/o transactions. when operating as a bus master, the hw3130 performs dma transactions, automatically transferring packet data between its internal fifos and the host memory using efficient burst transactions. homepna magnetics rj11 leds serial eeprom daa line codec optional v.90/v.92 lucent technologies home wire HW3100 homepna /modem controller lsio pci hw2000 afe i/o homepna 1.1 afe leds serial eeprom lucent technologies home wire hw2000 afe host-controlled modem afe
lucent technologies inc. 5 preliminary product brief HW3100/hw2000 home wire august 2000 home phoneline networking chip set functional description (continued) pci the HW3100 pci interface is fully compliant with pci local bus specification revision 2.2 and the pci power management interface specification. pci sub- system id, subvendor id, and vendor id are automati- cally read from the serial eeprom. the pci bus supports a 32-bit interface with an operating clock rate between dc and 33 mhz. hw2000 afe interface the HW3100 supports a 17-pin interface to the hw2000 afe. the interface consists of a two-phase, multiplexed data converter interface with control logic used to control the positioning of the msb of the data as well as the internal gain or attenuation of the hw2000 receiver and transmitter paths. serial eeprom interface the HW3100 supports a 4-pin serial interface to exter- nal eeprom. the minimum serial eeprom size is 512 bytes. integrated homepna 1.1 phy in order to provide backwards compatibility with exist- ing applications and home phoneline networks based on homepna 1.1 technology, the HW3100 supports an on-chip homepna 1.1 phy. the HW3100 supports a 4-pin 1m8 interface from the integrated phy port to the external resistive hybrid. media access controller (mac) the HW3100 supports an ieee 802.3-compliant media access controller. the mac offloads the host cpu and manages packet transmission, packet reception, and destination address filtering. jtag interface the HW3100 supports an ieee 1149.1 compliant jtag boundary-scan test access port interface. lsio interface the HW3100 chip set supports direct connection to either a line codec or the silicon labs * line codec/uni- versal daa. hw2000 overview the hw2000 is the analog front-end for the home wire chip set and provides the home pna 2.0 line interface functionality. the hw2000 is composed of the following functional blocks: n integrated crystal oscillator n 10-bit adc and dac n variable gain amplifiers n line drivers n filtering only minimal additional components (i.e., resistive hybrid, magnetics) are required to implement the homepna 2.0 line interface functionality. home wire chip set: support tools the primary HW3100/hw2000 home wire chip set evaluation tool is the HW3100/hw2000 home wire chip set pci reference design. the home wire pci reference design, bundled with drivers and installation software, will allow quick evaluation of the home wire chip set and support evaluation of interoperability. * silicon labs is a registered trademark of silicon laboratories, inc.
hw3 1 0 0 /hw 2 0 0 0 home wire preliminary product brief home phoneline net w orking chip set a ugust 2000 l u cent t echn o logies i n c. re s e r v es t h e r i g ht t o ma k e chan g es to t he p r oduct ( s) o r in f o r m ation c o ntain e d he r ein with o ut no t i c e . n o liability i s assum e d as a res u l t of t h eir us e or applicatio n . no rights u nde r a n y pa t ent acc o mpa n y the s a l e of a n y such p r oduct ( s) o r in f o r m a tion. home wire is a trademark of lucent technologies inc. co p yright ? 200 0 luce n t t ec h nologie s inc. all rights res e r v ed a ugust 20 0 0 p b 00-078hn e t f o r a d d i ti o n a l i n fo r m a t i o n , c o n ta c t y o u r m i c r o e l e c t r o n i c s g r o u p a cc o u n t m a n a ge r o r t h e f o l l o wi n g: i n terne t : http://ww w . lucent.com/mic r o e-m a il: do c m a ste r @mi c r o .lu c ent. c om n. a m erica : microelectronics grou p , lucent t echnologies i nc., 555 union boul e v ard, room 30l-15 p -ba, allent o wn , p a 18109-3286 1 - 80 0 - 37 2 - 2 4 4 7 , f a x 6 10 -7 1 2 - 4 1 06 ( i n c an a d a: 1 - 8 0 0 - 5 5 3 - 2 44 8 , f a x 6 1 0 - 71 2 - 4 1 06) asia p a cif i c : microelectronics grou p , lucent t echnologies singapore pt e . l t d. , 77 s cience p a r k d r i v e , #03-18 cintech iii , singapore 1 1 82 5 6 t el. ( 65 ) 7 7 8 8 8 33 , f a x ( 6 5 ) 7 7 7 74 9 5 c h i n a: m i c r o e l e c t r o n i cs g r o u p , l u c e n t t e c h n o l og i e s ( c h i n a ) c o . , lt d ., a - f 2 , 2 3 / f , z a o f o n g u n i v e rs e b u i l d i n g , 1 8 0 0 zh o n g s ha n x i ro a d, s h a n g ha i 2 00 2 3 3 p . r. c h i n a t e l . ( 8 6 ) 21 6 4 40 0 46 8 , e x t . 32 5 , f ax (8 6 ) 21 6 4 40 0 65 2 j a p a n: m i c r o e l e c t r o n i cs g r o u p , l u c e n t t e c h n o l og i e s j ap a n l t d ., 7 - 1 8 , h i ga s h i - g o ta n d a 2 -c h o m e , s h i n a g a w a - k u , t o k y o 1 4 1, j a p an t el. ( 81 ) 3 5 42 1 1 6 00 , f a x ( 8 1 ) 3 5 4 2 1 17 0 0 e u r o p e : d at a r e qu e s t s : m ic r o e l e c t r o n ic s g r ou p d a t a li n e : t e l. ( 4 4 ) 7 00 0 5 8 2 36 8 , f a x ( 4 4 ) 1 1 8 9 3 2 8 148 t e c h n i cal i n q u i r i e s : ge r ma n y : ( 4 9 ) 8 9 9 50 8 6 0 (m u n i c h ) , u n i t e d ki n gdo m : ( 4 4 ) 1 3 44 86 5 9 0 0 (ascot), f r a n ce : ( 3 3 ) 1 4 0 8 3 6 8 0 0 (p a r i s), s we d e n : ( 4 6) 8 5 9 4 6 07 00 (sto c k h o l m) , fi n land : ( 3 5 8 ) 9 3 5 07 6 7 0 ( h e l si n k i ), i t a l y : ( 3 9 ) 0 2 6 6 0 8 13 1 (milan), s p ain: ( 3 4 ) 1 8 0 7 1 4 4 1 (mad r id) home wire chip set product family overview t abl e 1. p r oduct feature matrix k e y : 3 : suppo r ted. : no t s u ppo r t e d. fe a tu r e hw 3 130 h w3 1 00 hw30 0 0s h w3 0 00m pci in t er f ac e , r e visio n 2.2 3 3 host-co n tr o lle d mo d em i nter f a ce 3 3 mic r oproces s o r -s l a v e inter f ace 3 mii 3 3 s e r ial e e prom in t er f ace 3 3 3 led int e r f ace 3 3 3 3 i nteg r a ted homepna revision 1.1 phy 3333 hw2 0 00 homepna 2.0 afe interface 3333 d e vice p a c k a ge 16 0 - p in mqfp 14 4 -pin tqfp 1 00-pin tqfp 10 0 - p i n tqfp
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